Architectures and Processors blog

.NET 9 introduces SVE support on Arm, allowing users to write simplified vectorised code. This blog post gives examples in C# and compares it to C++.

Supporting C++ style exceptions and DWARF for Pointer Authentication Codes (PAC) signed pointers.

Utilizing Pointer Authentication Codes (PAC) and Branch Target Instructions (BTI) together and optimizations in instruction counts.

This post will show how Linux developers can enable Pointer Authentication Codes (PAC) and Branch Target Instructions (BTI) them in C/C++ code bases.

How vendors can reduce cost and adapt to longer product lifecycles with an updated, compliance-based Arm SystemReady programme.

Arm's 2024 v9.6-A extensions introduce significant updates to enhance computing performance, efficiency, and security for today’s AI enabled software.

The SVMATCH instruction in Arm SVE2 accelerates multi-token string matches, boosting performance in tasks like JSON decoding.

This blog post explores three video and image use cases demonstrating the proven impact of the Armv9 CPU architectural features.

This blog post describes how to implement the same matrix-matrix multiplication algorithm using three different Arm technologies: Neon, SVE, and SME.

This blog is the second half of a two-part blog for SME Instructions. See link to Part 1 in the note at the top of this blog post.

This blog series provides an introduction to the Arm Scalable Matrix Extension (SME) including SVE and SVE2.

Upstream gem5 and ATP-Engine MPAM-style cache partitioning are discussed, with experiments for the feature being proposed and analyzed.

This blog covers techniques and tips that are useful to create better performing programs through compilers whether you are creating Android, Desktop or Server applications.

In-depth analysis of what the PMU of L2D_CACHE_WR counts on the Neoverse N2 server.

We refer to the SPE performance methodology whitepaper published by Arm for details on the content of this blog.

We discuss some of the challenges that we face when we are trying to implement the WebAssembly SIMD bitmask operations on the 64-bit Arm architecture.

This blog introduces how to profile firmware with Performance Monitor Unit (PMU) in Armv8-A CPU. It provides a reference implementation of the PMU library.

Views from the Arm technical leadership team that it believes that today, the cost implications of tightening C++ relaxed atomics outweigh its benefit.

This is the second and final part of the blog series on Dev Testing in .NET. In this part we look at further uses of SuperPMI and fuzzing with Fuzzlyn.

In part 1, we look at how .NET uses environment variables, some detailed IR dumps and SuperPMI.

The latest features and updates that have been added to Arm's A-Profile architecture in 2023.