I have some problems about his report when using ethous-U-vela.
The vela version I use is 3.0.0 . This is an introduction to Vela's options:review.mlplatform.org/.../OPTIONS.md
There is an example of Configuration File in the above website
I would like to ask
1.There are burst length and latency.
Does the latency in the example refer to memoey's CAS?
Then burst length refers to reading the address once, which can read several strokes continuously.
2.The three (Sram Only, Shared Sram, Shared Sram) modes that I want to ask the most are whether to adjust the four settings (const_mem_area, arena, cache_mem_area, arena_cache_size)) Instead of directly setting the model?
3.The total DRAM MB/batch in the figure below has a value.But there is no value in the last DRAM access cycle.What could be the problem?
4.Finally, I would like to ask about the value of those cycles. (Picture above)Where can I know the cycle value used by an OP?I think these values should be calculated after understanding the process of op operation.
Thank you for your answers in advance
for point 3: I checked the behaviour and it's align with the Vela code. Vela does DMA weight stored in Flash/DRAM (permanent storage) to SRAM, so that they are saved from reading more than once. That's why for the smaller you are getting 0 off chip flash cycles as weights are cached in SRAM. Hope this clears all your questions.