I am trying to find the location of the register where the timestamp generator can be enabled on a Cortex-M4 processor.
In the CoreSight SoC Technical Reference Manual on page 3-210 it is mentioned that the register (CNTCR) is in the PSELCTRL region (see image). However, I am not able to find the base memory address of this PSELCTRL region.
Can I find this address somewhere the ROM table that indicates the implemented debug components? But then how do I know which ID it is?
Or is it defined in some datasheet?
Thank you for any help.
STM32L433CC does not have the TSGEN, at least it is not listed in the manual.
AFAIK, the ROM table at 0xe00fF000, for each entry you have to look up the PIDs and compare them against the ones from the CoreSight manual in order to know what it is.
For example Jlink outputs this on a stm32l552:
CoreSight components: ROMTbl[0] @ E00FE000 ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB4C9 ROM Table ROMTbl[1] @ E00FF000 ROMTbl[1][0]: E000E000, CID: B105900D, PID: 000BBD21 Cortex-M33 ROMTbl[1][1]: E0001000, CID: B105900D, PID: 000BBD21 DWT ROMTbl[1][2]: E0002000, CID: B105900D, PID: 000BBD21 FPB ROMTbl[1][3]: E0000000, CID: B105900D, PID: 000BBD21 ITM ROMTbl[1][5]: E0041000, CID: B105900D, PID: 002BBD21 ETM ROMTbl[1][6]: E0042000, CID: B105900D, PID: 000BBD21 CTI ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BBD21 Cortex-M33
Dumping memory at 0xe00fe00:
J-Link>mem32 0xe00fe000,16 E00FE000 = 00001003 FFF42003 1FF02002 1FF02002 E00FE010 = 00000000 00000000 00000000 00000000
=> one entry at 0xe00fe000+0x1000 and one at 0xe00fe000+0xfff42000
Entries 2 and 3 are not present (LSB == 0)