Support forums

Architectures and Processors forum fixed Burst

State Accepted Answer
Locked Locked
Replies 2 replies
Subscribers 350 subscribers
Views 4289 views
Users 0 members are here

Options

How was your experience today?

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

fixed Burst

tom over 4 years ago

Hi All

here is the statement about fixed burst in axi spec.

The byte lanes that are valid are constant for all beats in the burst. However, within those byte
lanes, the actual bytes that have WSTRB asserted can differ for each beat in the burst.

if byte lanes that are valid are constant for all beats, the WSTRB signal should be same in all beats
why do the actual bytes that have WSTRB asserted can differ for each beat in the burst?
I am confused
Thanks!

Top replies

Colin Campbell over 4 years ago +1 verified

Hi Tom, Yes, the text could have been better worded. AWADDR and AWSIZE together tell you the data bus byte lanes that CAN be used for the first transfer in a transaction. For an INCR or WRAP burst...

Parents

0 tom over 4 years ago in reply to Colin Campbell

Thanks for your detail response.
Cancel
Up 0 Down

Cancel

Reply

0 tom over 4 years ago in reply to Colin Campbell

Thanks for your detail response.
Cancel
Up 0 Down

Cancel

Children

No data