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A72 Invalidate dirty cache line (DC IVAC)

uFedor

The A53 TRM says that when you invalidate a dirty cache line (DC IVAC), then a clean is automatically performed before the invalidate.

Does the A72 have the same behavior?

Is it possible to invalidate a dirty cache line without the clean happening?

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    ARM.ARM says:

    <quote>

    When executed at EL1, a DC IVAC instruction performs a clean and invalidate, meaning it performs the same
    maintenance as a DC CIVAC instruction, if all of the following apply:
    • EL2 is implemented and enabled in the current Security state.
    • The value of HCR_EL2.VM is 1, meaning EL1&0 stage two address translation is enabled.

    </quote>

    So I think it is impossible to invalidate a dirty cache line without the cleaning.

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  • 0

    ARM.ARM says:

    <quote>

    When executed at EL1, a DC IVAC instruction performs a clean and invalidate, meaning it performs the same
    maintenance as a DC CIVAC instruction, if all of the following apply:
    • EL2 is implemented and enabled in the current Security state.
    • The value of HCR_EL2.VM is 1, meaning EL1&0 stage two address translation is enabled.

    </quote>

    So I think it is impossible to invalidate a dirty cache line without the cleaning.

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