Within an arm system, a cluster is an ACE master connected to the Arm CCI. To keep the cache coherency, the cluster would send some transactions to the bus and are trapped by the snoop filter of CCI. For example, in Table 7-9 in 7.2.1 of A53 TRM, it says,
Could someone offer me more details about the error cases, how could those happen? How can a cluster actually evicts some data without sending the evict transactions?
Thank you so much :)
CPUs can have a programmable register that enables or disables Evicts being generated. So a software error might be that this register has not been set correctly.
It's also not an ACE protocol requirement that Evicts have to be sent for every line that is evicted, and so it's possible that in some scenarios a CPU may invalidate a line without issuing an Evict - for example, due to an ECC error.