Encounter a "undefined abort" exception during run-time sha256_compress(...) operation within following assembly sequence(captured from ELF binary's objdump):
"..........................
103d34: 5e282a30 sha256su0 v16.4s, v17.4s <<==== Exception triggered at this line and in JTAG debugger it shows as ==== ".word 5e282a30" 103d38: 4eb81f1a mov v26.16b, v24.16b 103d3c: 4ea18637 add v23.4s, v17.4s, v1.4s 103d40: 5e164338 sha256h q24, q25, v22.4s 103d44: 5e165359 sha256h2 q25, q26, v22.4s 103d48: 5e136250 sha256su1 v16.4s, v18.4s, v19.4s
............................"
I want to know root-cause for sure SO i could communicate to my vendor to get the issues resolved. Please help me understand the situation and below is my theory:
1. Running SOC is XIlinx Zynqmp ultrascale+ Cortex-A53 SoC and its specification indicates it's arm v8-a and supports Crypto Extension.
2. By reading ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0 SHA2, bits [15:12] ====> 0b0000, which indicates that "No SHA2 instructions implemented."
2> seems conflicting with what's claimed in its specification as 1>.
Here is my question: Is there possible to enable Crypto Extension supported on this SoC? Or, Crypto Extension feature has been disabled on my board as part of manufacturing provision process? Or, other reasons?
Much appreciated in advance!
Lei Zhou
Cortex-A53 is Armv8.0-A processor.
Armv8.0-A processors can support below crypto extension features:
The Armv8 Cryptographic Extension provides instructions for the acceleration of encryption and decryption, andincludes the following features:• ARMv8.0-AES, which includes AESD and AESE instructions.• ARMv8.0-SHA, which includes the SHA1* and SHA256* instructions.
Armv8.2-A processors can support other additional crypto extension features:
From Armv8.2, an implementation of the Armv8.0 Cryptographic Extension can include either or both of:• The AES functionality, including support for multiplication of 64-bit polynomials. The ID_AA64ISAR0_EL1.AES field indicates whether this functionality is supported.• The SHA1 and SHA2-256 functionality. The ID_AA64ISAR0_EL1.{SHA2, SHA1} fields indicate whether this functionality is supported.
Summary: SHA2 instruction is an Armv8.2-A crypto feature so that it is not supported in Armv8.0-A Cortex-A53.