I can't understand why there are separate registers like Interrupt Set-Enable and Clear-Enable Registers or Interrupt Set-Pending and Clear-Pending Register in NVIC? these dual registers couldn't be handled in just one? what are the reasons that ARM processors separate them in different registers?
Thanks! I get it. It's a really interesting trick.
In the arm processor implementation, there is just one register for Pending and the rest are connected to set/clear of the FF or three separate registers (Set-Enable, Clear-Enable, and Pending)?