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Architectures and Processors forum Interrupt latency while STR/LDR in cortex-M3

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Interrupt latency while STR/LDR in cortex-M3

Yaniv over 4 years ago

Hi,

What is the expected behaviour on M3 when issuing STR/LDR to some remote memory (AHB) and interrupt arrive? is the interrupt being delayed although this is normal memory and this command can re-run?

Thanks,

Yaniv

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0 42Bastian Schick over 4 years ago

AFAIK, normal loads and stores are not interruptible. Only load/store multiple.
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0 42Bastian Schick over 4 years ago

AFAIK, normal loads and stores are not interruptible. Only load/store multiple.
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