I'm using AXI VIP example design in Vivado 2020.1, Can anyone here explain how can I setup AWVALID, AWREADY, ARVALID, ARREADY.
My design is: AXI VIP master --> AXI Interconnect --> 4 BRAM controller --> 4 Single Port RAM (Block Memory Generator).
I'm not able to change the time of assertion or deassertion of control signals like AWVALID, AWREADY, ARVALID, ARREADY. I'm new in IP's and their example designs. So please guide me in from which file I could do it. As I'm not able to identify from where these control signals can be manipulated.
I'm using 4th simulation set: sim_basic_mst_active__pt_passive__slv_mem which is given in the example design.
Also, in the waveform, I'm getting delays which i could not relate from the Master Stimulus code given. There is no way I can change the delays which are available.
As it looks like Vivado is a Xilinx tool, you might be more likely to get help if you posted your question on Xilinx's forums.