coherence between R82 and other cpu or hardware modules

In the public datasheet of Cortex-R82

https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Arm_Cortex-R82_Processor_Datasheet.pdf?revision=702dda08-8ef9-4064-a461-293747c73a82&la=en&hash=9167E767B0899F607DB500F09197AA726FE180E4 

Cortex-R82 can support AXI or CHI-E Main Master port, if CHI-E is used, then with coherent interconnect, it supports hardware coherency for multiple Cortex-R82 clusters or Cortex-A clusters.

If you were talking about the cache coherency within cores in one Cortex-R82 cluster, then L2 memory system in the cluster is able to maintain cache coherency between them. 

If using Cortex-R82 ACP port, an ACE5-Lite 128-bit shared slave main Accelerator Coherency Port (ACP) for external access to MM address ranges. ACP enables I/O coherency for external agents with the per-core L1 data cache and shared L2 cache.

In the public datasheet of Cortex-R82

https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Arm_Cortex-R82_Processor_Datasheet.pdf?revision=702dda08-8ef9-4064-a461-293747c73a82&la=en&hash=9167E767B0899F607DB500F09197AA726FE180E4 

Cortex-R82 can support AXI or CHI-E Main Master port, if CHI-E is used, then with coherent interconnect, it supports hardware coherency for multiple Cortex-R82 clusters or Cortex-A clusters.

If you were talking about the cache coherency within cores in one Cortex-R82 cluster, then L2 memory system in the cluster is able to maintain cache coherency between them. 

If using Cortex-R82 ACP port, an ACE5-Lite 128-bit shared slave main Accelerator Coherency Port (ACP) for external access to MM address ranges. ACP enables I/O coherency for external agents with the per-core L1 data cache and shared L2 cache.