I have recently seen a problem with the L2 cache controller.
The L2 cache controller under the heavy memory load of a specific memory area, flush cache line (only part of it) to L3 - that means
The L2C-310 cache line length is 32-byte, by default -> e.g. 8/32 bytes are correctly flushed to L3
Im using cortex-a9 with the revision > r3. Only 1 CPU (handled with the lock) executes L2 clean&inval operation and waits until the operation is completed
Ive tried to use barriers to avoid prefetching, disabling L2 prefetching, ...
The problem is not deterministic and may happen on different memory areas, mostly near by the translation tables.
Do you have any idea why L2 clean&inval operation can flush only a few bytes from the cache line ?
I've checked recent Erratas, but I didnt find any information, which can relate to this problem. Is there any other reason why L2 clean&inval operation doesnt work properly ?
What cache maintenance is being used? Memory mapped L2 cache operation or cache CMO to PoC?