Defining power on execution state of LS1027A dual ARM Cortex A72 core SoC

I'm a hw designer and using Layerscape LS1027A dual Cortex A72 core SoC in a new design. The question is how this specific processor determines the execution state (AArch32 vs. AArch64) during boot time. According to the ARM specification  during powerup and on reset, the processor enters EL3, the highest Exception level. The Execution state for this Exception level is controlled by the configuration input signal, AA64nAA32. However, I have not found any further information on this AA64nAA32 signal. Is this a kind of hw signal I have to take care? How can I set the required state of this signal? I have not used ARM before, any inputs are much appreciated!