In AXI5 Atomic Transaction is there a facility that we can send address or data first?
I'd say the opposite, that you could send write data first.
The write data transfer isn't really relevant to the successful completion of the exclusive sequence, it would be the write address that is checked against other accesses.
But where leading write data would then be an issue is at the destination, where without an address you don't know what to do with that data. So the destination device might either buffer that write data, or it might hold WREADY low to stall the write data. But neither of them are relevant to the exclusive access mechanism.
So an exclusive write is just the same as a normal write, except that it must be preceded by a matching exclusive read, and obviously that it will have monitoring logic that might change the write response returned.
But that's all theoretical. The physical implementation of an exclusive access monitor might want to delay the W channel transfer completing until it has seen and checked the AW transfer, just to make things simpler or cleaner to process.