Cortex-A53 Data Cache line allocation without reading memory

Hi,

Is it possible to allocate a data cache line for the Cortex-A53 without triggering a read from memory?

When looking at the ARMv8-A architecture, the ARMv8-A reference manual has a note for the "DC ZVA" instruction saying:

"The architecture makes no statements about whether or not a DC ZVA instruction causes allocation to any particular
level of the cache, for addresses that have a cacheable attribute for those levels of cache."

However, the programmer's guide for ARMv8-A says the following:

"Cache line zeroing behaves in a similar fashion to a prefetch, in that it is a way of hinting to the
processor that certain addresses are likely to be used in the future. However, a zeroing operation
can be much quicker as there is no need to wait for external memory accesses to complete.
Instead of getting the actual data from memory read into the cache, you get cache lines filled
with zeros. It enables hinting to the processor that the code completely overwrites the cache line
contents, so there is no need for an initial read."

This seems like the exact thing that I need, but then the Cortex-A53 reference manual specifies the following:

"The ARMv8-A architecture introduces a Data Cache Zero by Virtual Address (DC ZVA) instruction. This enables a block of 64 bytes in memory, aligned to 64 bytes in size, to be set to zero.
If the DC ZVA instruction misses in the cache, it clears main memory, without causing an L1 or L2 cache allocation."

This does not seem to be in line of what the programmer's guide says the instruction should do.
On the one hand (ARMv8-A) it will allocate a cache line and not touch main memory (or read from it), in the case of the A53 it will just clear memory without allocating a cache line.

So is there another option to do a similar thing for the A53?

Kind regards