Is PendSV or counterpart available on Cortex-A?

Hi Ronan,

  Thanks for response.  I had read through learn_the_architecture_-_aarch64_exception_model, get much better understanding to the exception model of Cortex-A. I had worked on RTOS implementation for Cortex-M, what I'm interested is that, when supporting multi-thread in EL0, is there any mechanism in EL1 to do the function similar to PendSV?  More specifically, I wish to have a processor's feature, implemented in EL1, whenever an exception handler in EL1 decides a thread-context-switching needed, (multi-threads running in EL0), a lowest priority of IRQ in EL1 to be asserted and then at the very end of exception returning from EL1 to EL0, an tailed exception taken and thread-context-switching performed within. I thought the mechanism of PendSV  provides a very efficient pathway to start procedure of thread-context-switching.

PendSV, presents characters of  lowest priority, software caused, asynchronous.  

Thanks, Andy

Hi Ronan,

  Thanks for response.  I had read through learn_the_architecture_-_aarch64_exception_model, get much better understanding to the exception model of Cortex-A. I had worked on RTOS implementation for Cortex-M, what I'm interested is that, when supporting multi-thread in EL0, is there any mechanism in EL1 to do the function similar to PendSV?  More specifically, I wish to have a processor's feature, implemented in EL1, whenever an exception handler in EL1 decides a thread-context-switching needed, (multi-threads running in EL0), a lowest priority of IRQ in EL1 to be asserted and then at the very end of exception returning from EL1 to EL0, an tailed exception taken and thread-context-switching performed within. I thought the mechanism of PendSV  provides a very efficient pathway to start procedure of thread-context-switching.

PendSV, presents characters of  lowest priority, software caused, asynchronous.  

Thanks, Andy