Cacheable=0 vs Shareable=1

Hi,

I have R5F core with ARMv7 architecture. I want the memory to be shared across the multiple R5F CPUs in AM2732 TI device.

I am confused what happens if -

1. Cacheable = 1 and Shareable = 1
2. Cacheable = 0 and Shareable = 1
3. Cacheable = 0 and Shareable = 0
4. Cacheable = 1 and Shareable = 0

How does the CPU distinguishes between the same ?

Best Regards,
Aakash

PS. I suppose #2 should be sharable across CPUs and #4 should be done via software coherency. But what about the others really ?