could the Rready signal be asynchronous with aclk?

We can't comment on the behaviour of Xilinx VIP, but the AXI Specification requires that all the signals are synchronous with the clock associated with that interface.  From A3.3.1 in the AXI.K Specification

"Each AXI interface has a single clock signal, ACLK. All input signals are sampled on the rising edge of ACLK. All output signal changes can only occur after the rising edge of ACLK."

We can't comment on the behaviour of Xilinx VIP, but the AXI Specification requires that all the signals are synchronous with the clock associated with that interface.  From A3.3.1 in the AXI.K Specification

"Each AXI interface has a single clock signal, ACLK. All input signals are sampled on the rising edge of ACLK. All output signal changes can only occur after the rising edge of ACLK."