It is my understanding that the M0+ pipeline can fetch 2 16-bit instructions in a single cycle. Does that still apply if we branch to an address that isn't 32-bit aligned?
For example, if we branch to address 0x00302, will the M0+ on that next cycle fetch the instructions at both 0x00302 and 0x00304? Or will it only fetch 0x00302 on that cycle and then get 0x00304 and 0x00306 the next time?
The Cortex-M0+ will fetch 32-bit each time it performs an instruction fetch. However, as most Thumb instructions for CM0+ are 16-bits, it will fetch every other cycle.Branches breaks this steady-state pattern and could cause back-to-back instruction fetches depending on instruction address alignment. Branches to unaligned addresses require 2 back-to-back fetches to fill the pipeline with the target code – the first of these will be 16-bits while the second will be 32-bits (this differs from Cortex-M0, which always performs 32-bit instruction fetches).