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Data cache and I cache Memory allocation

Pragathi Simha

Hi,

We are using TI-AWR294x

As per the reference manual,

From CCSIR it is clear that it supports 16KB.

But how to make use of complete 16KB, no where we see an option to select it. All other registers are read only. By default it selects L1 cache and it shows 4KB.

Before enabling cache we also tried to overwrite CSOR (8KB for data, 8KB for instruction)as shown below, but still no change.

mov r1, #0x11
mcr p15, #0, r1, c15, c14, #0

And one input needed in the Register CSSELR, it mentions either of the cache can be selected. so how to select both.

Regards,

Pragathi Simha

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    The registers you are using report what the processor has, they don't control how the caches are divided up.

    To expand on that:

    • CLIDR reports the number of cache levels the processor has, and whether each level has a unified cache or separate instruction and data caches.
    • CCISDR reports information on the cache selected by CSSELR.
    • CSSELR selects one specific cache, using Level and InD.

    If a given Level has split caches, CCISDR isn't reporting the overall cache information for the level.  Rather it is information specifically for the cache selected by Level+InD.

    It is possible that for a level with split Instruction and Data caches that those caches are different sizes.  That's a design time decision, there's nothing software can do to override it.

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  • 0

    The registers you are using report what the processor has, they don't control how the caches are divided up.

    To expand on that:

    • CLIDR reports the number of cache levels the processor has, and whether each level has a unified cache or separate instruction and data caches.
    • CCISDR reports information on the cache selected by CSSELR.
    • CSSELR selects one specific cache, using Level and InD.

    If a given Level has split caches, CCISDR isn't reporting the overall cache information for the level.  Rather it is information specifically for the cache selected by Level+InD.

    It is possible that for a level with split Instruction and Data caches that those caches are different sizes.  That's a design time decision, there's nothing software can do to override it.

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