Hi Community!
■ Issue DescriptionErrors occur in the burst waveform when accessing external SRAM. The test conditions are as follows:
- MMU enabled
- Data cache disabled
- Page table of the external SRAM area set as cacheable (== write-back/read-write/allocate)
■ InquiryI'm inquiring whether it is permissible to access cacheable areas (== write-back/read-write/allocate) with the data cache disabled.
If anyone could help regarding this , then it would solve a long standing problem for me.
Regards
The CPU is able to access regions marked as cacheable when data cache is off, I measured that CPU speed would be 20X slower with data cache off.