We have a few security blocks along the way and we use Axuser to carry the security settings like Stream ID etc.
There is a security block in front of masters where they are supposed to change the User bits based on realms.
These security blocks should not add latency and hence do not implement a proper register slice (accept Axi and send Axi)
They combinatorially decide the User bits and send it out on the bus.
So is it okay that master sends say X and the block inbetween converts that to Y before mapping it to slave.
There is a slight rule we are possibly breaking where AxUser bits changing whilst valid is asserted ? Is that okay.
It's a while since I worked on AXI, but I think you're violating the handshaking used for transfers. From A3.2 in AMBA® AXI Protocol Specification rev K.
The source presents information after edge 1 and asserts the VALID signal as shown in Figure A3.2. The destination asserts the READY signal after edge 2. The source must keep its information stable until the transfer occurs at edge 3, when this assertion is recognized.
I think you'll face the problem of not knowing which version of the AxUSER signals the recipient actually saw.