I'm trying to perform a 64 bit write access to a certain memory (data access) located in the peripheral area using the M55 AXI bus.
I see the disassembly and it looks ok ("strd" command).
however, in the waves, I see that the M55 exported 2 AXI operation . each one is 32 bits width.
is there a way to configure it to export it with a single 64 bit operation instead of two 32 bits operations?
note that fetch access does generate a AXI 64 bit transaction . looks like it only related to data access.
For device memory the maximum burst length for write transfers is two, whereas for reads it is always a single transfer, this is mainly for interrupt latency purposes otherwise we would have to wait for the transfer to complete before taking the interrupt.
Section 10.4 "Manager-AXI interface" of the Cortex-M55 TRM shows different transactions (reads/writes) that the processor can generate to Normal and Device memory.
developer.arm.com/.../Manager-AXI-interface
So, 64-bit reads/writes can only be generated to Normal memory and not Device.
For example, if we executed a STRD to address 0x4000_0000 (Device memory), we would see the following:
AWSIZE=0x2 (4 bytes - 32-bit)AWLEN=0x1 (2 beats)On the first beat WSTRB would be set to 0x0F and on the next beat 0xF0
If the same instruction is executed to address 0x6000_0000 (Normal memory), we would see the following:
AWSIZE=0x3 (8 bytes - 64-bit)AWLEN=0x0 (1 beat)Write strobes set to 0xFF for the entire 64-bit write