I am working on testing the Error Detection and Correction (ECC) mechanisms of the A53 Cache. I am curious about when ECC detects bit flips, but the technical reference didn't mention it. Does ECC operate periodically and independently with the support of additional hardware resources, or does it only function during read/write operations?
Cortex-A53 STL got the below certification. Please talk with Arm Account Manager or Sales/FAE for your company to know more about the Cortex-A53 ECC.