Questions about Write Interleaving Exclusion in AXI4 Protocol

I am reaching out to seek the actual reason that write data interleaving is not supported in the AXI4 protocol.

As far as I know, in the AXI4 protocol, write data interleaving is no longer supported. Some argue that the effort and resources required to support write data interleaving were too high, which led to its exclusion from the AXI4 protocol. However, when multiple masters with different transmission speeds attempt to perform write transactions simultaneously, the interconnect can become congested if write data interleaving is not supported. This could decrease the bandwidth and throughput of the bus.

So, what is the actual reason that write interleaving is not supported in the AXI4 protocol if there is potential performance degradation in some common scenarios? Are there any other pros and cons that need to be considered? And what exactly are the efforts and resources needed to support write interleaving?