Hi,
I am working on FPGA platform having 1 cluster of A725 with 3 cores. I am running QNX on cluster-0/core-0 without HYP. While QNX kernel booting, I am getting data abort exception 0x96000035 (unsupported exclusive or atomic access) when executing a specific instruction, CASAL, in the following process and setting.
[Steps]
bit[5:0] 0b110101 means IMPLEMENTATION DEFINED fault (Unsupported Exclusive or Atomic access).
In step 4, the ESR_EL1 shows that an unsupported exception is triggered when executing the casal instruction, but in step 1, the capability retrieved from the CPU register indicates that it is supported. Two information are conflict. After attempting to run QNX without LSE flag rising, it runs normally.
Can anybody give hint on the issue?
The code (Unsupported Exclusive or Atomic access) isn't saying that CASAL is not supported, rather that the address the instruction operated on doesn't support Exclusives/Atomics.
Oversimplifying a bit, there's broadly two ways atomics/exclusives are handled.
For cacheable locations, the ensuring of exclusivity/atomicity is handled by the caches and cache coherency. That's required to work (see B2.17.2 of the Arm ARM, rev K.a).For non-cacheable locations, the core puts out the appropriate AMBA transfer and relies on the memory system to manage exclusivity/atomicity. Whether a given SoC can do that, and if "yes" for which addresses, is up to the SoC designer. If software attempts an atomic/exclusive to a non-cacheable location, and the memory system doesn't support those access types for that location, you get the syndrome code you reported.
You said the MMU is enabled, are the caches (SCTLR_ELx.C)? If yes, what are the attributes for the address being accessed by the CASAL?