As the address for the subsequent transfers is calculated by slave, then there is no need of ARVALID/ARREADY and AWVALID/AWREADY for subsequent transfers.
1) So can these signals take any logic level or need to be logic high level for the rest of the burst ? Is ARADDR is updated with new address calculated by slave for subsequent transfer ?
2) Master can drive next valid write data only after WVALID and WREADY are asserted at same rising edge. Which means, only after the last write date is received by slave(indicated by assertion of WVALID and WREADY at same rising edge), master can drive valid write data. Pls confirm.
Amit Mishra said:1) So can these signals take any logic level or need to be logic high level for the rest of the burst ? Is ARADDR is updated with new address calculated by slave for subsequent transfer ?
Ax below refers to either AR or AW.
AxVALID indicates the information on the Ax bus is valid, and that the manager interface is attempting to issue this information downstream. AxREADY indicates that the subordinate can accept the information, and a transfer will occur when AxREADY and AxVALID = 1.
This means that for a single AXI transaction, AxVALID will be 1 until the information on the Ax bus is transferred - when AxREADY = 1. After this point, AxREADY can be either high or low - it depends on whether the subordinate interface could accept another transfer. AxVALID will be 0, unless the manager interface wishes to send another transaction.
See the example below:
Amit Mishra said:2) Master can drive next valid write data only after WVALID and WREADY are asserted at same rising edge. Which means, only after the last write date is received by slave(indicated by assertion of WVALID and WREADY at same rising edge), master can drive valid write data. Pls confirm.
I'm not quite sure I understand this question. Potentially the example above clarifies this?