Dear sirs,
I read ACE specification and ARM processor documents for ACP explanation. I always have some questions about ACP.
As soon as you know, ACP exists in SCU for data coherency.
Q1: The document says that ACP usually connects to a DMA or cryptographic engine, so why does it connect to them?
Q2: who starts ACP port to transfer data from where to where?
Q3: How does ACP implement coherency in multi-core processor?
Thanks.
Cray
Not sure I follow. If for example the ACP port is part of MPCore Processors and has an outbound AXI slave interface than it is for external Masters, eg. DMA, to help coherency for within that MPCore Processors, that is DMA can allocate to the L2 of that MPcore Processors.
I also understand the ACP port may/may not be included but if not the amount of CMOs is greater.