ARM Cortex A-8 Bare-metal application with uboot

Hi,

In Beaglebone Black I'm trying to run a baremetal program (UART0 running in polling mode) from SDCard.

I'm using Uboot as Second stage bootloader to load and run the baremetal program and it is configured with default config “am335x_evm_defconfig”.

Compiled both Uboot and baremetal program with ARM toolchain gcc-arm-none-eabi-10.3-2021.10. Copied MLO, u-boot.img and helloworld.bin (baremetal program) to the SD-Card.

Baremetal program is written without vector table as FIQ and IRQ are disabled.

With reference to AM335x ARM® Cortex -A8 Microprocessors TRM, I found the below RAM addresses to load the application from uboot.

From section 2.1 ARM Cortex A8 Memory Map

• EMIF0 SDRAM - Start_address (0x8000_0000), End_address(0xBFFF_FFFF), Size(1GB)  - 8-/16-bit External Memory

From section 26.1.3.2 Public RAM Memory Map

• Public RAM memory map ranges from address 0x402F0400h to 0x4030FFFFh on a GP Device

I'm trying to load and run the baremetal application from both RAM address, both are not working as expected.

Load application to the RAM address 0x402f0400 from uboot:

$ fatload mmc 0 0x402f0400 helloworld

getting on fatload command "trying to overwrite reserved memory…"

Loading and running application from RAM address 0x80000000 from uboot:

$ fatload mmc 0 0x80000000 helloworld

$ go 0x80000000

baremetal program is running, but soon the target is restarting.

Below is the start-up code of the bare-metal application:

.globl _start

_start:
mrs r0, cpsr
bic r0, r0, #0x1F ;@ clear mode bits
orr r0, r0, #0x13 ;@ set SVC mode
orr r0, r0, #0xC0 ;@ disable FIQ and IRQ
msr cpsr, r0

mrc p15,0,r0,c1,c0,2 ;@ read cp access register
orr r0,r0,#0x00F00000 ;@ enable full access to neon/vfp (coproc 10&11)
mcr p15,0,r0,c1,c0,2 ;@ write cp access register
isb ;@ instruction synchronization barrier
mov r0,#0x40000000 ;@ switch on vfp & neon
vmsr fpexc,r0 ;@ set EN bit in fpexc

ldr sp, =0x4030CDFC ;@6kB public stack TRM 26.1.3.2, used when copying and running the program from  the RAM address 0x402f0400,
//ldr sp, =0x8030CDFC ;used when copying and running the program from  the RAM address 0x80000000
bl psr_main

.loop: b .loop

Below is the linker script of the baremetal program:

MEMORY
{
//RAM : ORIGIN = 0x80000000, LENGTH = 0x1B400 // used when copying and running the program from  the RAM address 0x80000000
RAM : ORIGIN = 0x402f0400, LENGTH = 0x1B400 // used when copying and running the program from  the RAM address 0x402f0400,
}

SECTIONS
{
	.text :
	{
		*(.text*);
	}> RAM

	.data :
	{
		*(.data*);
	}> RAM

	.bss :
	{
		*(.bss*);
	}> RAM
}

I'm new to the bare-metal programming and Cortex-A8 architecture and it's memory mapping.

I would like to get feedback from the ARM experts.

Please let me know any more details are needed from my side.

Please guide me.

Thanks.