Cache control in Cyclone V HPS

Hi,

I am on Cyclone V HPS development using Arm tool chain v6.
I am trying to define a data buffer in non-cacheable memory region.

Is there any example or application note to configure linker script(.scat) to define non-cacheable external RAM region ?
Please note that I don't want to disable L1 and L2 caches completely.

Best Regards,
Naresh

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Ronan Synnott 11 days ago +1 suggested

Hello Naresh Scatterloading defines the execution address, but not the cacheable status. You would need to configure the MMU such that this region is non-cacheable. Regards, Ronan

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0 Naresh Rajput 10 days ago in reply to Ronan Synnott

Thanks Ronan for the quick reply.

Is there any example available to define non-cacheable region in MMU configuration ?

Best Regards,
Naresh
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0 Naresh Rajput 10 days ago in reply to Ronan Synnott

Thanks Ronan for the quick reply.

Is there any example available to define non-cacheable region in MMU configuration ?

Best Regards,
Naresh
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