Cache control in Cyclone V HPS

Hi,

I am on Cyclone V HPS development using Arm tool chain v6.
I am trying to define a data buffer in non-cacheable memory region. 

Is there any example or application note to configure linker script(.scat) to define non-cacheable external RAM region ?
Please note that I don't want to disable L1 and L2 caches completely.

Best Regards,
Naresh

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