How does Mali GPU implement the RO/WO registers?

Arm Mali GPU expose their registers to CPU side using MMIO. And there are so many types of registers (written in device drivers' source code) which are used for different usages. How does Mali GPU check the register access permissions?

I tested on Hikey960 Development Board using busybox devmem, there are some MMIO registers (GPU_ID, GPU_FEATURE, etc.) which are not writable from CPU side. I wonder how does hardware implement read-only/write-only permissions on this registers?

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Peter Harris 4 months ago +1 verified

Config registers are physically read-only hardware, they are not programmable. As they are memory mapped, read permission is controlled by CPU page tables.

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+1 Peter Harris 4 months ago

Config registers are physically read-only hardware, they are not programmable.

As they are memory mapped, read permission is controlled by CPU page tables.
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+1 Peter Harris 4 months ago

Config registers are physically read-only hardware, they are not programmable.

As they are memory mapped, read permission is controlled by CPU page tables.
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