This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cornex M0 M3 M4 NVIC bugs. Number one.

Hi fellows!

Excuse my english.

I have a NVIC bug on stm32f030F4 revision codes A, stm32f051C8 rc B, stm32f100RB rc Z, stm32f303VC rc Y
This is assembler code for stm32f051C8

				GET		../inc/stm32f0xx.asm

Stack_Size      *     0x00000400

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       %	   Stack_Size
__initial_sp

                PRESERVE8
                THUMB

                AREA    RESET, DATA, READONLY
                GLOBAL  __Vectors

__Vectors       &     __initial_sp
                &     Reset_Handler
                &     NMI_Handler
                &     HardFault_Handler
                &     0
                &     0
                &     0
                &     0
                &     0
                &     0
                &     0
                &     SVC_Handler
                &     0
                &     0
                &     PendSV_Handler
                &     SysTick_Handler

                &     WWDG_                     ;1		0x00
                &     PVD_                      ;2
                &     RTC_                      ;4
                &     FLASH_                    ;8
                &     RCC_                      ;16
                &     EXTI0_1_                  ;32
                &     EXTI2_3_                  ;64
                &     EXTI4_15_                 ;128
                &     TSC_                      ;1		0x01
                &     DMA1_Channel1_            ;2
                &     DMA1_Channel2_3_          ;4
                &     DMA1_Channel4_5_          ;8
                &     ADC1_COMP_                ;16
                &     TIM1_BRK_UP_TRG_COM_      ;32
                &     TIM1_CC_                  ;64
                &     TIM2_                     ;128
                &     TIM3_                     ;1		0x02
                &     TIM6_DAC_                 ;2
                &     0
                &     TIM14_                    ;8
                &     TIM15_                    ;16
                &     TIM16_                    ;32
                &     TIM17_                    ;64
                &     I2C1_                     ;128
                &     I2C2_                     ;1		0x03
                &     SPI1_                     ;2
                &     SPI2_                     ;4
                &     USART1_                   ;8
                &     USART2_                   ;16
                &     0
                &     CEC_                      ;64


                AREA    mainCode, CODE, READONLY

Reset_Handler    PROC
                 GLOBAL  Reset_Handler

;Initilization Port А USART2
				ldr		r0,=0x40021000				;RCC_CR
				movs	r1,#2_10				
				strb	r1,[r0,#0x16]				;set bits IOPAEN&IOP in RCC_AHBENR
				movs	r1,#2_10
				strb	r1,[r0,#0x1E]				;set bit USART2EN in RCC_APB1ENR
;set division APB/(0...16)
				movs	r1,#0x04
				strb	r1,[r0,#0x05]
;Configure io pins
				ldr		r0,=0x48000000				;GPIOA_MODER
				movs	r1,#4_2210
				strb	r1,[r0]						;PA1 as OUT push-pull
				ldr		r1,=0x1100
				strh	r1,[r0,#0x20]				;PA1-TX PA2-RX
;Enable extern interrupt on pin PA0
				cpsid	i
				ldr		r0,=0xE000E100				;NVIC_ISER
				ldr		r1,=(0x20+0x08000000)
				str		r1,[r0]						;enable EXTI0_1_ & USART1_
				ldr		r0,=0x40010400				;EXTI_IMR
				ldr		r1,=0x0F940001
				str		r1,[r0]						;interrupt on pin0 is't masked
				movs	r1,#1
				str		r1,[r0,#0x08]				;interrupt on risig
				str		r1,[r0,#0x14]				;clear pending interrupt on pin A0 - just in case :)
				cpsie	i

				
				B		.
				ALIGN
				ENDP

EXTI0_1_		PROC
				cpsid		i
				ldr		r2,=0x48000018				;GPIOA_BSRR
				movs	r1,#2_10
				strb	r1,[r2]
				ldr		r0,=0x40004428				;USART2_TDR
				movs	r1,#2_01010101
				str		r1,[r0]
				ldr		r1,=0x7A1200
LedIRQ
				subs	r1,#1
				BNE		LedIRQ
				movs	r1,#2_10
				strb	r1,[r2,#0x02]
				ldr		r0,=EXTI_PR
				movs	r1,#1
				str		r1,[r0]
				cpsie	i

				BX		LR
				ALIGN
				ENDP

NMI_Handler		PROC
                GLOBAL  NMI_Handler
                B       .
                ENDP
HardFault_Handler	PROC
                GLOBAL  HardFault_Handler
                B       .
                ENDP
SVC_Handler     PROC
                GLOBAL  SVC_Handler
                B       .
                ENDP
PendSV_Handler  PROC
                GLOBAL  PendSV_Handler
                B       .
                ENDP
SysTick_Handler PROC
                GLOBAL  SysTick_Handler
                B       .
                ENDP

Default_Handler PROC

                GLOBAL  WWDG_
                GLOBAL  PVD_
                GLOBAL  RTC_
                GLOBAL  FLASH_
                GLOBAL  RCC_
                GLOBAL  EXTI0_1_
                GLOBAL  EXTI2_3_
                GLOBAL  EXTI4_15_
                GLOBAL  TSC_
                GLOBAL  DMA1_Channel1_
                GLOBAL  DMA1_Channel2_3_
                GLOBAL  DMA1_Channel4_5_
                GLOBAL  ADC1_COMP_
                GLOBAL  TIM1_BRK_UP_TRG_COM_
                GLOBAL  TIM1_CC_
                GLOBAL  TIM2_
                GLOBAL  TIM3_               
                GLOBAL  TIM6_DAC_
                GLOBAL  TIM14_
                GLOBAL  TIM15_
                GLOBAL  TIM16_
                GLOBAL  TIM17_
                GLOBAL  I2C1_
                GLOBAL  I2C2_
                GLOBAL  SPI1_
                GLOBAL  SPI2_
                GLOBAL  USART1_
                GLOBAL  USART2_
                GLOBAL  CEC_


WWDG_
PVD_
RTC_
FLASH_
RCC_
;EXTI0_1_
EXTI2_3_
EXTI4_15_
TSC_
DMA1_Channel1_
DMA1_Channel2_3_
DMA1_Channel4_5_
ADC1_COMP_
TIM1_BRK_UP_TRG_COM_
TIM1_CC_
TIM2_
TIM3_
TIM6_DAC_
TIM14_
TIM15_
TIM16_
TIM17_
I2C1_
I2C2_
SPI1_
SPI2_
USART1_
USART2_
CEC_

                B       .
                ENDP
                ALIGN
				END

LED connect to PA1, button to PA0. When I press the button, the LED is lit for 4 second, if PPRE[2:0] =  0 or 2_100. If PPRE[2:0] = 2_101 and hight LED is lin 8 sec.

Parents Reply Children
No data