• State Not Answered
  • Locked Locked
  • Replies 1 reply
  • Subscribers 26 subscribers
  • Views 3802 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Morello FVP for bare metal - SCP Firmware build issue

Raj

As stated in the Morello Bare Metal debug example, the necessary changes were made in the scp firmware code's specified file to start the rainier cores from 0x14000000

Now to Build the SCP firmware for PRODUCT=morello, 

1. compiling using CC=arm-none-eabi-gcc, builds the firmware but for the resulting FVP invoked as per bare metal documentation states: 

> SCP Firmware -> Module Initialization Complete

> Invalid FIP ToC header nme: [0x20040000]

> Failed to locat SCP_BL2, error -1

And running the program gives error, no function named main could be found.

The guide states "For all products other than host, the code needs to be compiled by a cross-compiler"

2. Setting CC=clang-11 and SYSROOT to the bin directory of the morello llvm baremetal toolchain release 1.1 fails. Clang-11 command not found.

also make SYSROOT=/opt/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/aarch64-none-elf CC=clang-11 PRODUCT=morello does not work (after installing the gcc-arm aarch)

What is the right compiler to use for Morello FVP to build scp firmware

Parents
  • 0

    Hello Raj,

    Are you trying to rebuild the SCP firmware to run the Morello bare-metal examples?
    The instructions for building and running those examples have changed significantly since the initial Arm DS Morello release.

    Since around late March or so, the SCP firmware no longer needs to be modified and rebuilt to run the examples. You can now use the standard integrated stack build, and the SCP bare-metal use case is now supported through the model launch script only.

    With that being said, you don't need to rebuild the standard SCP firmware if you already have it, but you can if you explicitly want to.
    To build the standard SCP firmware, you can follow the instructions provided here, in "doc/cmake_readme.md:"
    https://github.com/ARM-software/SCP-firmware

    You can also build the required "scp_fm.bin" and "mcp_fw.bin" from instructions listed here:

    https://git.morello-project.org/morello/docs/-/blob/morello/mainline/user-guide.rst

    The files should be generated after following the steps at "Board Support Package Stack with Poky distribution".

    Lastly, the updated instructions to run the bare-metal example (which will be included in the next official release of the Arm DS Morello Edition in the future):

    -----------------------------------------------------------------------------------------------------------------------------

    Morello bare-metal debug - Arm®Development Studio

    This example tutorial shows how to use the Morello FVP model and SCP/MCP firmware for running/debugging the bare-metal Morello examples ("bubblesort" and "fireworks").

    Purpose and scope

    This example tutorial shows how to use the Morello FVP model and System Control Processor (SCP) and Manageability Control Processor (MCP) firmware for running/debugging the bare-metal Morello examples ("bubblesort" and "fireworks").
    It is assumed that you have already downloaded the 'LLVM compiler with Morello support', the Morello FVP model, the SCP/MCP firmware source code, and the GCC compiler to build the SCP/MCP firmware. Also, that you have added the Morello FVP model folder to the PATH, and compiled the SCP/MCP firmware with GCC to generate scp_romfw.bin, mcp_romfw.bin, scp_fw.bin and mcp_fw.bin.
    There are two further steps:
    1. Obtain the "branch-to-self" binary bts.bin that is used to make the Rainier cores execute a wait loop at address 0x14000000
    2. Launch the Morello FVP model with the SCP/MCP firmware and "branch-to-self" binary.

    Obtain the "branch-to-self" binary bts.bin that is used to make the Rainier cores execute a wait loop at address 0x14000000

    For information on how to build and use the "branch-to-self" binary bts.bin, please refer to the "bts" example project.
    A ready-made plain binary bts.bin is provided.

    Launch the Morello FVP model with the SCP/MCP firmware and "branch-to-self" binary

    This section describes how to launch the Morello FVP model so that it is suitable for running bare-metal Morello examples.
    1. Ensure that telnet or xterm is installed on your system. This is needed to show the serial output from the SCP and MCP firmware.
    2. Launch the Morello FVP model with all the parameters needed to boot the firmware, with:
      FVP_Morello --plugin=MTS.so --data Morello_Top.css.scp.armcortexm7ct=/path/to/scp_romfw.bin@0x0 --data Morello_Top.css.mcp.armcortexm7ct=/path/to/mcp_romfw.bin@0x0 -C Morello_Top.soc.scp_qspi_loader.fname=/path/to/scp_fw.bin -C Morello_Top.soc.mcp_qspi_loader.fname=/path/to/mcp_fw.bin -C css.scp.armcortexm7ct.INITVTOR=0x0 -C css.mcp.armcortexm7ct.INITVTOR=0x0 --data=/path/to/bts.bin@0x14000000 -C soc.scc.boot_gpr_2=0x14000000 -C soc.scc.boot_gpr_3=0 -C css.cluster0.cpu0.semihosting-heap_base=0 -C css.cluster0.cpu0.semihosting-heap_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_base=0x81000000 --run --cadi-server
    3. Wait a few seconds for the platform setup to be completed by the SCP and MCP firmware running on the Cortex-M7s.
    4. You can now connect the Debugger, as described in the readmes for the "bubblesort" and "fireworks" examples.
    Explanation of the parameters:
    • FVP_Morello is the basic Morello platform model.
    • --plugin=MTS.so (optionally) adds support for instruction trace.
    • scp_romfw.bin, mcp_romfw.bin, scp_fw.bin and mcp_fw.bin are the SCP/MCP firmware that the Cortex-M7s execute to setup the platform.
    • INITVTOR=0x0 sets the Cortex-M7's VTOR to 0x0.
    • --data=bts.bin@0x14000000 loads at 0x14000000 the ready-made plain binary executable bts.bin that contains a single "branch to self" instruction. When firmware execution reaches 0x14000000, code execution sits in an endless loop until the Debugger connects to the model and stops code execution.
    • semihosting-stack/heap_base/limit sets the base and limit of the stack and heap, for semihosting programs. The C library startup code uses these values to initialize the stack and heap correctly, together with their appropriate capabilities.
    • --run tells the model to start running the SCP and MCP firmware immediately.
    • --cadi-server tells the model to launch a CADI server, to which the Debugger will subsequently connect.
    You can disable the graphical HDLCD and M7s visualization if you wish by adding the parameter -C disable_visualisation=1.

    Running the example on the command-line

    You can also run an executable on the Morello FVP model directly from the command-line (outside the Debugger) by first processing it with the make-bm-image.sh utility provided with the 'LLVM compiler with Morello support', for example:
    make-bm-image.sh -i image.elf -o bm_image.elf
    then launching the Morello model with the processed executable, for example:
    FVP_Morello --data Morello_Top.css.scp.armcortexm7ct=/path/to/scp_romfw.bin@0x0 --data Morello_Top.css.mcp.armcortexm7ct=/path/to/mcp_romfw.bin@0x0 -C Morello_Top.soc.scp_qspi_loader.fname=/path/to/scp_fw.bin -C Morello_Top.soc.mcp_qspi_loader.fname=/path/to/mcp_fw.bin -C css.scp.armcortexm7ct.INITVTOR=0x0 -C css.mcp.armcortexm7ct.INITVTOR=0x0 --data=/path/to/bm_image.elf@0x14000000 -C soc.scc.boot_gpr_2=0x14000000 -C soc.scc.boot_gpr_3=0 -C css.cluster0.cpu0.semihosting-heap_base=0 -C css.cluster0.cpu0.semihosting-heap_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_base=0x81000000
    You can disable the graphical HDLCD and M7s visualization if you wish by adding the parameter -C disable_visualisation=1.
Reply
  • 0

    Hello Raj,

    Are you trying to rebuild the SCP firmware to run the Morello bare-metal examples?
    The instructions for building and running those examples have changed significantly since the initial Arm DS Morello release.

    Since around late March or so, the SCP firmware no longer needs to be modified and rebuilt to run the examples. You can now use the standard integrated stack build, and the SCP bare-metal use case is now supported through the model launch script only.

    With that being said, you don't need to rebuild the standard SCP firmware if you already have it, but you can if you explicitly want to.
    To build the standard SCP firmware, you can follow the instructions provided here, in "doc/cmake_readme.md:"
    https://github.com/ARM-software/SCP-firmware

    You can also build the required "scp_fm.bin" and "mcp_fw.bin" from instructions listed here:

    https://git.morello-project.org/morello/docs/-/blob/morello/mainline/user-guide.rst

    The files should be generated after following the steps at "Board Support Package Stack with Poky distribution".

    Lastly, the updated instructions to run the bare-metal example (which will be included in the next official release of the Arm DS Morello Edition in the future):

    -----------------------------------------------------------------------------------------------------------------------------

    Morello bare-metal debug - Arm®Development Studio

    This example tutorial shows how to use the Morello FVP model and SCP/MCP firmware for running/debugging the bare-metal Morello examples ("bubblesort" and "fireworks").

    Purpose and scope

    This example tutorial shows how to use the Morello FVP model and System Control Processor (SCP) and Manageability Control Processor (MCP) firmware for running/debugging the bare-metal Morello examples ("bubblesort" and "fireworks").
    It is assumed that you have already downloaded the 'LLVM compiler with Morello support', the Morello FVP model, the SCP/MCP firmware source code, and the GCC compiler to build the SCP/MCP firmware. Also, that you have added the Morello FVP model folder to the PATH, and compiled the SCP/MCP firmware with GCC to generate scp_romfw.bin, mcp_romfw.bin, scp_fw.bin and mcp_fw.bin.
    There are two further steps:
    1. Obtain the "branch-to-self" binary bts.bin that is used to make the Rainier cores execute a wait loop at address 0x14000000
    2. Launch the Morello FVP model with the SCP/MCP firmware and "branch-to-self" binary.

    Obtain the "branch-to-self" binary bts.bin that is used to make the Rainier cores execute a wait loop at address 0x14000000

    For information on how to build and use the "branch-to-self" binary bts.bin, please refer to the "bts" example project.
    A ready-made plain binary bts.bin is provided.

    Launch the Morello FVP model with the SCP/MCP firmware and "branch-to-self" binary

    This section describes how to launch the Morello FVP model so that it is suitable for running bare-metal Morello examples.
    1. Ensure that telnet or xterm is installed on your system. This is needed to show the serial output from the SCP and MCP firmware.
    2. Launch the Morello FVP model with all the parameters needed to boot the firmware, with:
      FVP_Morello --plugin=MTS.so --data Morello_Top.css.scp.armcortexm7ct=/path/to/scp_romfw.bin@0x0 --data Morello_Top.css.mcp.armcortexm7ct=/path/to/mcp_romfw.bin@0x0 -C Morello_Top.soc.scp_qspi_loader.fname=/path/to/scp_fw.bin -C Morello_Top.soc.mcp_qspi_loader.fname=/path/to/mcp_fw.bin -C css.scp.armcortexm7ct.INITVTOR=0x0 -C css.mcp.armcortexm7ct.INITVTOR=0x0 --data=/path/to/bts.bin@0x14000000 -C soc.scc.boot_gpr_2=0x14000000 -C soc.scc.boot_gpr_3=0 -C css.cluster0.cpu0.semihosting-heap_base=0 -C css.cluster0.cpu0.semihosting-heap_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_base=0x81000000 --run --cadi-server
    3. Wait a few seconds for the platform setup to be completed by the SCP and MCP firmware running on the Cortex-M7s.
    4. You can now connect the Debugger, as described in the readmes for the "bubblesort" and "fireworks" examples.
    Explanation of the parameters:
    • FVP_Morello is the basic Morello platform model.
    • --plugin=MTS.so (optionally) adds support for instruction trace.
    • scp_romfw.bin, mcp_romfw.bin, scp_fw.bin and mcp_fw.bin are the SCP/MCP firmware that the Cortex-M7s execute to setup the platform.
    • INITVTOR=0x0 sets the Cortex-M7's VTOR to 0x0.
    • --data=bts.bin@0x14000000 loads at 0x14000000 the ready-made plain binary executable bts.bin that contains a single "branch to self" instruction. When firmware execution reaches 0x14000000, code execution sits in an endless loop until the Debugger connects to the model and stops code execution.
    • semihosting-stack/heap_base/limit sets the base and limit of the stack and heap, for semihosting programs. The C library startup code uses these values to initialize the stack and heap correctly, together with their appropriate capabilities.
    • --run tells the model to start running the SCP and MCP firmware immediately.
    • --cadi-server tells the model to launch a CADI server, to which the Debugger will subsequently connect.
    You can disable the graphical HDLCD and M7s visualization if you wish by adding the parameter -C disable_visualisation=1.

    Running the example on the command-line

    You can also run an executable on the Morello FVP model directly from the command-line (outside the Debugger) by first processing it with the make-bm-image.sh utility provided with the 'LLVM compiler with Morello support', for example:
    make-bm-image.sh -i image.elf -o bm_image.elf
    then launching the Morello model with the processed executable, for example:
    FVP_Morello --data Morello_Top.css.scp.armcortexm7ct=/path/to/scp_romfw.bin@0x0 --data Morello_Top.css.mcp.armcortexm7ct=/path/to/mcp_romfw.bin@0x0 -C Morello_Top.soc.scp_qspi_loader.fname=/path/to/scp_fw.bin -C Morello_Top.soc.mcp_qspi_loader.fname=/path/to/mcp_fw.bin -C css.scp.armcortexm7ct.INITVTOR=0x0 -C css.mcp.armcortexm7ct.INITVTOR=0x0 --data=/path/to/bm_image.elf@0x14000000 -C soc.scc.boot_gpr_2=0x14000000 -C soc.scc.boot_gpr_3=0 -C css.cluster0.cpu0.semihosting-heap_base=0 -C css.cluster0.cpu0.semihosting-heap_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_limit=0x80800000 -C css.cluster0.cpu0.semihosting-stack_base=0x81000000
    You can disable the graphical HDLCD and M7s visualization if you wish by adding the parameter -C disable_visualisation=1.
Children
No data