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In AXI-5, can BVALID be asserted on same cycle as WLAST?

Sagar Shah

Hi,

AMBA AXI specification (version K) section A3.5.1 says,

"The Subordinate must also wait for WLAST to be asserted before asserting BVALID. This wait is because the write response, BRESP, must be signaled only after the last data transfer of a write transaction."

I couldn't find a statement in specification which says asserting BVALID and WLAST at the same time is prohibited.

Can you please confirm whether it is allowed to assert BVALID on same cycle as WLAST or not?

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    This would be illegal, and the very text you quote would be the statement in the specification that tells you this would not be legal.

    WLAST, along with WVALID, would be asserted in the final data transfer of a transaction. The subordinate would then sample this final WDATA transfer when WREADY is also high, and only then can BVALID be asserted to signal a write transaction response.

    Note that WVALID/WREADY/WLAST all high would be sampled on the next rising edge of ACLK, after which the subordinate could then assert BVALID, so there is at least a one cycle delay from WLAST/WVALID being asserted to when BVALID can be asserted.

    Also note that WLAST asserted without WVALID is meaningless, so it is when both WLAST and WVALID are asserted that a final data transfer is being indicated. WLAST could be asserted after the second last transfer in the transaction, but before WVALID is asserted, and WLAST would only be considered valid when WVALID is also high. So it is WLAST/WVALID together that is important, not just WLAST.

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    This would be illegal, and the very text you quote would be the statement in the specification that tells you this would not be legal.

    WLAST, along with WVALID, would be asserted in the final data transfer of a transaction. The subordinate would then sample this final WDATA transfer when WREADY is also high, and only then can BVALID be asserted to signal a write transaction response.

    Note that WVALID/WREADY/WLAST all high would be sampled on the next rising edge of ACLK, after which the subordinate could then assert BVALID, so there is at least a one cycle delay from WLAST/WVALID being asserted to when BVALID can be asserted.

    Also note that WLAST asserted without WVALID is meaningless, so it is when both WLAST and WVALID are asserted that a final data transfer is being indicated. WLAST could be asserted after the second last transfer in the transaction, but before WVALID is asserted, and WLAST would only be considered valid when WVALID is also high. So it is WLAST/WVALID together that is important, not just WLAST.

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